1. Technical Field
The present invention relates generally to a nonvolatile memory device, and more particularly, to a nonvolatile memory device which manages an erase count and an operating method is thereof.
2. Related Art
Semiconductor memory devices are generally divided into a volatile memory device and a nonvolatile memory device. While the volatile memory device requires power supply to retain stored data, the nonvolatile memory device can retain stored data even in absence of power supply. Nonvolatile memory devices include various types of memory cell transistors. Nonvolatile memory devices are divided into a flash memory device, a ferroelectric RAM (FRAM), a magnetic RAM (MRAM), a phase change RAM (PRAM), etc.
Among nonvolatile memory devices, flash memory devices are generally divided into a NOR flash memory device and a NAND flash memory device, depending upon a configuration of memory cells and a bit line. The NOR flash memory device has a configuration in which two or more memory cell transistors are connected in parallel to one bit line. Accordingly, the NOR flash memory device has an excellent characteristic in terms of random access time. Conversely, the NAND flash memory device has a structure in which two or more memory cell transistors are connected in series to one bit line. This configuration is referred to as a cell string structure, and one bit line contact is needed per a cell string. Therefore, the NAND flash memory device has an excellent characteristic in terms of the degree of integration.
A memory system including a flash memory device may is uniformly manage the wear levels of the pages or blocks of the flash memory device so that the flash memory device can be used with reliability for a long time. That is, the memory system may manage the wear levels of the pages or blocks of the flash memory device so that the data is distributed evenly across the memory cells even if a user repeatedly writes data to the same logical sector, and this is referred to as a wear leveling technique. In using the wear leveling technique, the memory system may manage an erase count for each of the blocks of the flash memory device. The memory system may manage the erase count through a working memory, and may also back up the erase count to the flash memory device.